Nowadays, multi-standard broad band transceiver, is an emerging topology in cellular telecommunication systems. Moreover, high performance is required with several difficult standards among the targeted applications. The issue is further complicated by requirements on more compact form factor and on design approaches toward more integration. Moreover, Complementary Metal Oxide Semiconductor (CMOS) low quality factor (low-Q) components are limiting the performance of many circuit techniques. Consequently new architectures and circuit techniques must be explored.
To address some of the mentioned issues, In-phase and Quadrature-phase (I/Q) modulator and Harmonic Rejection Mixers (HRM) have recently gained attention. Indeed the vast majority of transceivers fall into I/Q modulator based receivers and transmitters. These modulators use In-phase and Quadrature-phase mixers (I/Q mixers). I/Q mixers address the problem of maximizing information transmission in a limited bandwidth by allowing the user to modulate both the in-phase and quadrature phase components of a carrier simultaneously, doubling the information density.
In order to drive an I/Q mixer, in one approach, a divider able to create 25% duty cycle signals from an externally supplied clock at 2*fLO is often used, where fLO is the frequency of local oscillator (LO) signal input to the mixer. Such a divider is disclosed in a conference paper by Ivan Fabiano et al., “SAW-less analog front-end receivers for TDD and FDD”, ISSC2013, p 82-p 85. The divider according to Fabiano utilizes a latch disclosed in the same paper.
A divider which generates 25% duty cycle signals is in the art often called a 4-phase signal generator.
The divider and latch disclosed by Fabiano are derived from a circuit disclosed in an article by Behzad Razavi et al., “Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS”, IEEE journal of solid-state circuits, vol. 30, No. 2, February 1995. In the article several novel circuits are disclosed.
In general, there are potential timing problems associated with the latch circuit disclosed by Razavi. Even though the circuit operates properly in a specific scope of application, the circuit poses timing uncertainty in general, i.e. in latch mode of operation, there is a possibility of overriding the stored state in the circuit.
Conventional switching mixers introduce relatively large harmonics at multiples of Radio Frequency (RF) signal input and/or RF signal output frequency of transceivers, demanding filtering in specific locations of the signal chain in the transceivers. Indeed the aforementioned 4 phase signals in an I/Q modulator has a harmonic suppression/conversion effect. The fact that the I/Q mixer samples with the quadrature LO signals results in image rejection for each harmonic, however the remaining odd harmonics on the antenna port will reradiate and/or down converted to baseband. This is because even in receivers, passive mixers which are bidirectional type of mixers, will back up-convert baseband signals present on capacitors in baseband circuits during each LO cycle. In other words out of band interferers at odd harmonics of the LO signals will be down converted to baseband. Odd harmonics reradiate as well from antenna in receivers after back up-conversion and radiate in transmitters after conversion. Hence suppression of the out of band interferers and suppression of direct radiation of odd harmonics by filtering or HRM will be essential for performance. However, substantial cost saving could be achieved by removal or reducing the filter's performance. In wideband systems the issue is more important to tackle. This is because e.g. in a wideband low noise amplifier (LNA) in the receiver, interferers will be amplified with lower selectivity in the signal chain. It is thus important to suppress the 3rd and higher order harmonic.
The HRM based transceivers mainly address bandwidth, selectivity and filtering metrics in emerging wireless communication. Nowadays, almost all HRM-based transceivers use I/Q type of modulators for purpose of image rejection and bandwidth efficiency.
Among the different orders of the harmonics, the 3rd order harmonic is the most critical one to remove. The rejection of the 3rd order harmonic may be done by a six-phase harmonic rejection mixer. However, the 6-phase harmonic rejection mixer needs a clock driver which can deliver six pulse signals with 60 degrees consecutive phase difference in-between, hereafter referred as 6-phase signals. The 6-phase signals should have either a non-overlapped duty cycle of 16.7% or an overlapped duty cycle of 33.3% to drive the mixer. However, generation of the 6-phase signals with 16.7% duty cycle directly is of prime importance for high performance, e.g. lower noise in receivers, to avoid accomplishing the action of commutating from 33.3% duty cycle pulses to 16.7% duty cycle pulses in mixer switches.
Harmonic rejection mixers up to 5th order may be realized as 8-phase mixers for suppression of 3rd and 5th harmonics. However a 6-phase mixer in receiver which mainly suppresses 3rd harmonic is considered as a more practical approach to an 8-phase and higher order multi-phase mixers.
The generation of 6-phase signals may be implemented as a division locking structure as described in Raul Magoon et. al., RF local oscillator path for GSM Direct conversion transceiver with true 50% divided by three and active third harmonic cancellation, IEEE Radio Frequency Integrated Circuits Symposium, 2002, and in A. Nejdel, et. al., A 0.7-3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection, European Solid State Circuits Conference (ESSCIRC) 2013.
In these prior art design approaches, and in the former case the on-chip local oscillator (LO) multi-phase signal generation circuitry is clocked by a differential external signal at three times the desired LO frequency. The function of division and phase generation is accomplished by three double-edge triggered D flip-flops, implemented in current mode logic (CML) in bipolar technology. The output signals of the divider are 50% duty cycle LO signals, phase shifted by 60 degree with respect to one another. Further, in the latter design approach, the output signals are generated by laches implemented in CML-to-CMOS logic level converter, and then CMOS logic is used to generate either 16.7% or 33.3% duty cycle signals. The major drawback of the mentioned prior art approaches is high power consumption of CML type of circuit and limited high frequency operation. The low jitter noise in these design approaches as an important metric, is improved by relatively high current capability of involved active devices with relatively large idle DC current. The involved active devices fulfill jitter noise requirement, but tend to be large with more parasitic and hence have limited highest operating frequency. An additional consequence is large total current consumption which results in larger DC—as well as larger dynamic—power dissipation. The generation of 6-phase signals may also be implemented by injection locking as described in C. Zhou, et. al., A 50% wide locking range divide by 3 up to 6 GHz, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2011. The injection locked approach uses frequency dependent tuning components, which is inherently band limited. Indeed with this type of circuit structure, it is hard to pass an operating frequency limit higher than 7 GHz even though relatively fast 65 nm device technology was used in benchmarking of the circuit performance.
In addition to the applications mentioned above, where 4-phase signals and 6-phase signals are needed for the I/Q mixers and HRM in 6-phase mixers in the transceivers, higher order multi-phase signals, e.g. 8, 10, 12, . . . 32, . . . may be needed in future transceivers or for other applications in other electronic devices, e.g. oscillator scopes, measurement instruments etc.